High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips (e.g., dice) vertically and interconnecting the chips using through substrate vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface and vertically stacked DRAM. A typical HBM stack of four DRAM chips (e.g., core chips) has two 128-bit channels per chip for a total of eight input/output channels and a width of 1024 bits in total. An interface (I/F) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. For example, a clock frequency, a command sequence, and data can be independently provided for each channel. Thus, the eight input/output channels are not necessarily synchronous to each other.
There are several types of tests which may be performed for the HBM. For example, a type of test can be performed using a memory Built-In Self Test (mBIST) circuit that may be provided on the I/F chip. The mBIST circuit is provided for verifying failures resulting from stacking the chip. The mBIST circuit may include a memory to store defect information called an error-catch memory (ECM). Using the defect information, for example, hard repair such as blowing fuse to disconnect rows and columns with faulty bits and replacing them with redundant rows or columns may be performed.
The HBM has a post package repair function performed by using the mBIST circuit. The post package repair function uses redundancy cells for repair and these redundancy cells are normally formed in memory matrices of the core. However, the post package repair function may not be able to repair defects if the number of defective cells is greater than a number of repairable cells by providing redundancy cells. Furthermore, it may be difficult to repair one or more defective cells which are redundancy cells.